Khác biệt giữa bản sửa đổi của “RAM tĩnh”
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'''Bộ nhớ truy cập ngẫu nhiên tĩnh''' ('''SRAM''' hay '''RAM tĩnh''') là một loại bộ nhớ sử dụng công nghệ [[bán dẫn]]. Từ "tĩnh" nghĩa là bộ nhớ vẫn lưu dữ liệu nếu có điện, không như [[RAM động]] cần được nạp lại thường xuyên. Không nên nhầm RAM tĩnh với [[bộ nhớ chỉ đọc]] và [[bộ nhớ flash]] vì RAM tĩnh chỉ lưu được dữ liệu khi có điện.
==Design==
[[Image:6t-SRAM-cell.png|thumb|300px|A six-transistor CMOS SRAM cell.]]
[[Random access]] means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
Each [[bit]] in an SRAM is stored on four [[transistor]]s that form two cross-coupled [[logical not|inverter]]s. This storage cell has two stable states which are used to denote '''0''' and '''1'''. Two additional ''access'' transistors serve to control the access to a storage cell during read and write operations. It thus typically takes six [[MOSFET]]s to store one memory bit.
Access to the cell is enabled by the word line (WL in figure) which controls the two ''access'' transistors M<sub>5</sub> and M<sub>6</sub> which, in turn, control whether the cell should be connected to the bit lines: <span style="border-top: 1px solid">BL</span> and BL. They are used to transfer data for both read and write operations. While it's not strictly necessary to have two bit lines, both the signal and its inverse are typically provided since it improves [[noise margin]]s.
During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM speed compared to [[Dynamic Random Access Memory|DRAMs]]—in a DRAM, the bit line is connected to storage capacitors and [[charge sharing]] causes the bitline to swing upwards or downwards. The symmetric structure of SRAMs also allows for [[differential signalling]], which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.
The size of an SRAM with ''m'' address lines and ''n'' data lines is 2<sup>''m''</sup> words, or 2<sup>''m''</sup> × ''n'' bits.
{{rất sơ khai}}
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